Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis

In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional circuits, it will not be recoverable, as a result, the circuits are provided based on the reversible logic and according to reversible gates for data retrieval. Since comparators are one of the basic building blocks in digital logic design, in which they compare two numbers, the aim of this research is to design a 1-bit comparator building block based on reversible logic and implement it in the QCA with the minimum cell consumption, less occupied area, and lower latency, as well as to design it in a single layer. The proposed 1-bit reversible comparator is denser, cost-effective, and more efficient in quantum cost, power dissipation, and the main QCA parameters than that of previous works.