TY - GEN
T1 - Custom DC-DC converters for distributing power in SLHC trackers
AU - Allongue, B.
AU - Buso, S.
AU - Blanchot, G.
AU - Faccio, F.
AU - Fuentes, C.
AU - Mattavelli, P.
AU - Michelis, S.
AU - Orlandi, S.
AU - Spiazzi, G.
PY - 2008
Y1 - 2008
N2 - A power distribution scheme based on the use of on-board DC-DC converters is proposed to efficiently distribute power to the on-detector electronics of SLHC trackers. A comparative analysis of different promising converter topologies is presented, leading to the choice of a magnetic-based buck converter as a first conversion stage followed by an on-chip switched capacitors converter. An overall efficiency above 80% is estimated for the practical implementation proposed. The above considerations lead to separate analog and digital power domains to be provided to SLHC tracker's staves1. In fact an additional domain will be needed, because optoelectronics components at the end(s) of the stave will require a voltage of at least 2.5V. The 2.5V will possibly be needed also by the stave and hybrid controller ASICs, in particular for the Input/Output (I/O) circuitry. The presence of 2 voltages on-chip, 2.5V for the I/O and 1.2V (or less) for the core, is a normal feature of advanced commercial digital circuits, and is commonly supported by CMOS technologies.
AB - A power distribution scheme based on the use of on-board DC-DC converters is proposed to efficiently distribute power to the on-detector electronics of SLHC trackers. A comparative analysis of different promising converter topologies is presented, leading to the choice of a magnetic-based buck converter as a first conversion stage followed by an on-chip switched capacitors converter. An overall efficiency above 80% is estimated for the practical implementation proposed. The above considerations lead to separate analog and digital power domains to be provided to SLHC tracker's staves1. In fact an additional domain will be needed, because optoelectronics components at the end(s) of the stave will require a voltage of at least 2.5V. The 2.5V will possibly be needed also by the stave and hybrid controller ASICs, in particular for the Input/Output (I/O) circuitry. The presence of 2 voltages on-chip, 2.5V for the I/O and 1.2V (or less) for the core, is a normal feature of advanced commercial digital circuits, and is commonly supported by CMOS technologies.
UR - https://www.scopus.com/pages/publications/84855182965
M3 - Conference contribution
AN - SCOPUS:84855182965
SN - 9789290833246
T3 - Proceedings of the Topical Workshop on Electronics for Particle Physics, TWEPP 2008
SP - 289
EP - 293
BT - Proceedings of the Topical Workshop on Electronics for Particle Physics, TWEPP 2008
PB - CERN
T2 - Topical Workshop on Electronics for Particle Physics, TWEPP 2008
Y2 - 15 September 2008 through 19 September 2008
ER -