Design and analysis of fault‐tolerant 1:2 demultiplexer using quantum‐dot cellular automata nano‐technology

Quantum‐dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manu-factured by QCA technology can provide a notable decrease in size, rapid‐switching velocity, and ultra‐low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault‐tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illus-trates a novel QCA‐based fault‐tolerant 1:2 demultiplexer construct that employs a two‐input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault‐tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner sim-ulator. The simulation results demonstrated that our proposed QCA‐based fault‐tolerant 1:2 demul-tiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault‐tolerant 1:2 demultiplexer could attain high fault‐tolerance when single missing cell or extra cell faults exist in the QCA layout.